User:Xaltonon

Out of the vast array of toys available from MechComp dispensers, one of the most confusing to newer mechanics is the Control Unit. It's a neat little device that can be programmed to accomplish a wide array of tasks. The MC14500B Industrial Control Unit is the real-life analogue of it.

Architecture

Registers

Registers are the memory of the microprocessor. There are several registers in the Control Unit. First, is RR, or the Result Register. It can only store one bit (0 or 1). Second, is the Input register. There are 8 inputs, labelled 0 through 7. They can be toggled on and off by sending a 0 or a 1 to the corresponding MechComp input. Input 0 is special, as it cannot be toggle on or off externally. It is always the complement (inverse) of RR. Lastly, there is the RAM. It has 8 bits of storage, again labelled 0 through 7. There is one other register, the Output register. It is write only, and has outputs 0 through 7. Values written to it are passed on (if the output is enabled) to other devices with the format Output Number:Output, eg. if you write the bit 1 to output 3, it will produce the signal 3:1. Two one-bit registers IEN and OEN are input enable and output enable flag bits respectively. If disabled, the input register cannot be read from and the output register and RAM cannot be written to.

Opcodes

The Control Unit has a ROM in hexadecimal that stores the program. The program loops after it finishes running. A command looks like this: Opcode, Operand. The processor chunks the ROM into pairs of bytes and execute them. These are the commands:

Mnemonic	Hex	Operand	Description
NOP	0	No	Does nothing. (Waits)
LD	1	Input	Loads a value from the input number in the operand, and stores it in RR. Operands 0-7 are the input register. The RAM is accessed by the upper 8 operands (8-F).
LDC	2	Input	Same as LD, but it takes the complement of the input and stores that.
AND	3	Input	Takes the value from the input specified in the operand and computes the logical AND of RR and the input. The result is stored in RR.
ANDC	4	Input	Same as AND, but takes the complement of the input.
OR	5	Input	Takes the value from the input specified in the operand and computes the logical OR of RR and the input. The result is stored in RR.
ORC	6	Input	Same as OR, but takes the complement of the input.
XNOR	7	Input	Takes the value from the input specified in the operand and computes the logical XNOR of RR and the input. The result is stored in RR.
STO	8	Output	Stores the value of RR in the output specified in the operand. Operands 0-7 are the output register. The RAM is accessed by the upper 8 operands (8-F).
STOC	9	Output	Same as STO, but stores the complement of RR.
IEN	A	Input	Sets the IEN flag to the input specified in the operand.
OEN	B	Input	Sets the OEN flag to the input specified in the operand.
JMP	C	Jump Amount	Jumps over an amount of bytes (in the ROM) determined by the operand. Operands 0-7 will add one to the operand, then jump backwards 4x that amount. Operands 8-F will subtract 7 from the operand, then jump forwards 4x that amount.
RTN	D	No	Jumps over the instruction following itself.
SKZ	E	No	Skips the next instruction if RR is zero.
NOP	F	No	Does nothing. (Waits)